Πλοήγηση ανά Θέμα "Pipeline processing systems"
Αποτελέσματα 1-9 από 9
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Extracting coarse-grained pipelined parallelism out of sequential applications for parallel processor arrays
(2009)We present development and runtime support for building application specific data processing pipelines out of sequential code, and for executing them on a general purpose platform that features a reconfigurable Parallel ... -
A Hybrid Approach to Hand Detection and Type Classification in Upper-Body Videos
(2019)Detection of hands in videos and their classification into left and right types are crucial in various human-computer interaction and data mining systems. A variety of effective deep learning methods have been proposed for ... -
Instruction-based timing analysis in pipelined processors
(2019)Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless ... -
Instruction-Flow-Based Timing Analysis in Pipelined Processors
(2019)Microprocessor design utilizes timing analysis in order to establish the maximal operation clock speed of the circuit. In static timing analysis, clock frequency is set in accord with the worst-case delay in the circuit ... -
Low power general purpose loop acceleration for NDP applications
(2020)Modern processor architectures face a throughput scaling problem as the performance bottleneck shifts from the core pipeline to the data transfer operations between the dynamic random access memory (DRAM) and the processor ... -
An open web services - Based framework for data mining of biomedical image data
(2009)Mining of biomedical image data is a complex procedure that requires several processing phases, such as data acquisition, preprocessing (e.g., image enhancement, color processing), feature extraction and classification. ... -
Performance and power simulation of a functional-unit-network processor with Simplescalar and Wattch
(2015)Loop acceleration is a means to enhance performance of a singleor multiple-issue microprocessor core. A new edge-like processor architecture incorporates a loop accelerator directly in the out-oforder back end of the ... -
Room-localized spoken command recognition in multi-room, multi-microphone environments
(2017)The paper focuses on the design of a practical system pipeline for always-listening, far-field spoken command recognition in everyday smart indoor environments that consist of multiple rooms equipped with sparsely distributed ... -
Supporting multitasking of pipelined computations on embedded parallel processor arrays
(2009)This paper presents software support that enables seamless task restructuring and load balancing of pipelined applications at runtime, making it possible to dynamically pick the stages that will be executed as separate ...