Instruction-based timing analysis in pipelined processors

Abstract

Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless of the possible circuit inputs. Dynamic analysis approaches are calculating delays using varying circuit inputs, but are in general very slow. Recent approaches to static timing analysis are based on better-than-worst-case algorithms, which attempt to trade-off the pessimism of standard static analysis with the optimism of dynamic analysis.The work presented in this paper is concentrated on an enhanced implementation of static timing analysis for processor design, applying dynamic analysis through specific variations of circuit inputs. In particular, given that the circuit inputs are mostly instructions of the processor instruction set, we have chosen to vary the instruction opcode of that input. Thus, we have designed and implemented a timing analysis algorithm, which produces timing information for each instruction of the processor, allowing the designer to focus on improving the architecture of particular instructions rather than redesigning circuit parts.We have tested our algorithm on an OpenRISC processor design and collected timing information through an innovative use of the Synopsis PrimeTime tool. A comparison against timing information obtained through pure static timing analysis makes clear that our algorithm succeeds to give better-than-worst-case timing for the most common instructions, thus allowing the designer to deliver a better product. © 2019 IEEE.