Supporting multitasking of pipelined computations on embedded parallel processor arrays

Abstract

This paper presents software support that enables seamless task restructuring and load balancing of pipelined applications at runtime, making it possible to dynamically pick the stages that will be executed as separate tasks on distinct CPUs, depending on the currently available resources and the execution context. This functionality is integrated in a development and execution framework for pipelined applications targeted at reconfigurable (in terms of interconnections), heterogeneous (in terms of architecture and/or clock speed), distributed memory, embedded Parallel Processor Arrays (PPAs). The primary motivation for this work is to support the use of PPA on-chip architectures, which are currently considered as dedicated accelerators, in a multitasking execution context where the available processor cores are distributed among concurrently executing applications. As a proof-of-concept, we discuss the execution of two pipelined applications on an FPGA-based prototype platform that features Xilinx Microblaze soft processor arrays. © 2009 IEEE.