Design of Reconfigurable Fault-Tolerant Datapaths

Abstract

In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, such as design for fault-tolerance against permanent and transient faults, design for improved manufacturability, and design of application specific programmable processors. This paper focuses on design techniques for efficient Reconfigurable Datapaths and thus directly addresses all three applications formerly mentioned. The approach is based on the flexibility of behavioral-level synthesis to explore the design space and the observability provided by Self-Checking circuits. A behavioral-level synthesis technique is developed and studied, that is through assignment and scheduling at the coarse-grain level of implementation. © 2020 IEEE.