Sfoglia per Soggetto "Integrated circuit design"
Items 1-19 di 19
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Asynchronous sub-threshold ultra-low power processor
(2015)Ultra low power VLSI circuits may enable applications such as medical implants, sensor networks and things for IoT. Aggressive supply voltage scaling is known to significantly improve power consumption and efficiency, but ... -
Conventional and machine learning approaches as countermeasures against hardware trojan attacks
(2020)Every year, the rate at which technology is applied on areas of our everyday life is increasing at a steady pace. This rapid development drives the technology companies to design and fabricate their integrated circuits ... -
Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs
(2022)Convolution Neural Networks (CNNs) are gaining ground in deep learning and Artificial Intelligence (AI) domains, and they can benefit from rapid prototyping in order to produce efficient and low-power hardware designs. The ... -
Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios
(2022)Standard-cell placement is the fundamental step in a typical VLSI/ASIC design flow. Its result, paired with the outcome of the routing procedure can be the decisive factor in rendering a design manufacturable. Global ... -
High-Level Annotation of Routing Congestion for Xilinx Vivado HLS Designs
(2021)Ever since transistor cost stopped decreasing, customized programmable platforms, such as field-programmable gate arrays (FPGAs), became a major way to improve software execution performance and energy consumption. While ... -
A High-Performance Neuron for Artificial Neural Network based on Izhikevich model
(2019)Neuromorphic circuits have gained a lot of interest through the last decades since they may be deployed in a large spectrum of scientific research. In this paper a hardware realization of a single neuron targeting Field ... -
Instruction-based timing analysis in pipelined processors
(2019)Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless ... -
Instruction-Flow-Based Timing Analysis in Pipelined Processors
(2019)Microprocessor design utilizes timing analysis in order to establish the maximal operation clock speed of the circuit. In static timing analysis, clock frequency is set in accord with the worst-case delay in the circuit ... -
Juxtaposing Vivado Design Flows in Batch Mode
(2021)Re-configurable hardware devices are at the forefront of technological advancement and academic research, with their most prominent delegate being Field Programmable Gate Arrays (FPGAs). A typical FPGA design cycle may ... -
Low power general purpose loop acceleration for NDP applications
(2020)Modern processor architectures face a throughput scaling problem as the performance bottleneck shifts from the core pipeline to the data transfer operations between the dynamic random access memory (DRAM) and the processor ... -
Low power monolithic 3D IC design of asynchronous AES core
(2015)In this paper, we demonstrate, for the first time, that a monolithic 3D implementation of an asynchronous AES encryption core can achieve up to 50.3% footprint reduction, 25.7% improvement in power, 34.3% shorter wirelength ... -
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis
(2022)Traditional processor architectures utilize an external DRAM for data storage, while they also operate under worst-case timing constraints. Such designs are heavily constrained by the delay costs of the data transfer between ... -
Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs)
(2016)Efficient analysis of on-chip power delivery networks is one of the most challenging problems facing the electronic design automation industry today. The fast dc and transient simulation of power grids is necessary to ... -
Parallelised Multithreaded Applications on a 4-core Field Programmable Gate Array (FPGA) Architecture
(2022)Background: The challenges in real-time multithreading, particularly in the efficiency of multithreaded applications running concurrently on multiple cores, have evolved significantly due to the increase in IoT, cloud and ... -
Performance and power simulation of a functional-unit-network processor with Simplescalar and Wattch
(2015)Loop acceleration is a means to enhance performance of a singleor multiple-issue microprocessor core. A new edge-like processor architecture incorporates a loop accelerator directly in the out-oforder back end of the ... -
QoS and MPLS design issues in NoCs
(2018)Nowadays real application traffic, and especially streaming applications running in multi core environments require more and more bandwidth. Networks on Chips (NoC) should be able not only to provide adequate bandwidth ... -
Rack-scale disaggregated cloud data centers: The dReDBox project vision
(2016)For quite some time now, computing systems servers, whether low-power or high-end ones designs are created around a common design principle: the main-board and its hardware components form a baseline, monolithic building ... -
Radiation Hardening Legalisation Satisfying TMR Spacing Constraints with Respect to HPWL
(2020)Reduction in device feature sizes and supply voltage renders modern Integrated Circuits (ICs) more susceptible to Soft Errors (SEs), i.e. Transient Faults caused by ionising radiation. Moreover, the RADiation HARDening ... -
SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems on Chip
(2016)Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. ...