Juxtaposing Vivado Design Flows in Batch Mode

Abstract

Re-configurable hardware devices are at the forefront of technological advancement and academic research, with their most prominent delegate being Field Programmable Gate Arrays (FPGAs). A typical FPGA design cycle may consist of multiple runs considering each available option targeting conflicting quality-of-result characteristics, based on a set of constraints, that narrows down the number of feasible implementations. Thus, prior knowledge of each strategy's performance might be considered rather useful from a designer's perspective. This paper presents a comparative study considering all available synthesis and implementation strategies of Xilinx's Vivado Design Suite, and tries to pinpoint key characteristics that may be effective in view of future endeavors. © 2021 ACM.