dc.creator | Mahdi A.S., Archonta C., Tzimas G., El-Kady A. | en |
dc.date.accessioned | 2023-01-31T08:55:53Z | |
dc.date.available | 2023-01-31T08:55:53Z | |
dc.date.issued | 2019 | |
dc.identifier | 10.1109/PACET48583.2019.8956264 | |
dc.identifier.isbn | 9781728143606 | |
dc.identifier.uri | http://hdl.handle.net/11615/76117 | |
dc.description.abstract | An architecture enabling a flexible on-board simulation and verification method for complex user-specific IPs is presented. The proposed method relies on an FPGA-SoC implementation of a golden simulation and verification model, properly optimized for simplicity and efficiency. It is designed to facilitate the integration of any VLSI-intended circuit into the FPGA-SoC board by a simple drag-and-drop fashion. Exploiting the SoC architecture of Xilinx Zynq-FPGA boards, the proposed method can also be used for SW-HW co-simulation flows by data-transferring between a Host-PC SW environment and the VLSI user's circuits. The data-exchange is based on an Ethernet connection between the host and the ARM Processor on the Zynq FPGA platform. The performance of a digital baseband transceiver system incorporating VLSI IPs of interest has been studied using the flexibility and reliability of the proposed hybrid SW-HW modelling method. © 2019 IEEE. | en |
dc.language.iso | en | en |
dc.source | 5th Panhellenic Conference on Electronics and Telecommunications, PACET 2019 | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85078952330&doi=10.1109%2fPACET48583.2019.8956264&partnerID=40&md5=fb8e01c1e2d05aa29b1ea743ba009600 | |
dc.subject | ARM processors | en |
dc.subject | Electronic data interchange | en |
dc.subject | Field programmable gate arrays (FPGA) | en |
dc.subject | Transceivers | en |
dc.subject | VLSI circuits | en |
dc.subject | Cosimulation | en |
dc.subject | Ethernet connections | en |
dc.subject | SoC architecture | en |
dc.subject | SoC implementation | en |
dc.subject | Verification method | en |
dc.subject | Verification model | en |
dc.subject | VLSI | en |
dc.subject | Zynq | en |
dc.subject | System-on-chip | en |
dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
dc.title | A SoC-ZYNQ-Based SW-HW Co-Simulation and Verification Method | en |
dc.type | conferenceItem | en |