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Efficient Circuit Reduction in Limited Frequency Windows

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Auteur
Floros G., Evmorfonoulos N., Stamoulis G.
Date
2019
Language
en
DOI
10.1109/SMACD.2019.8795231
Sujet
Integrated circuit manufacture
Timing circuits
Balanced truncation
Circuit reduction
Efficient simulation
Error estimates
Frequency windows
Model order reduction
Reduced order models
Specific frequencies
Circuit simulation
Institute of Electrical and Electronics Engineers Inc.
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Résumé
Model Order Reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on Balanced Truncation (BT) offer very good error estimates and can provide compact models with any desired accuracy over the whole range of frequencies (from DC to infinity). However, in most applications the circuit is only intended to operate at specific frequency windows, which means that the reduced-order model can become unnecessarily large to achieve approximation over all frequencies. In this paper, we present a frequency-limited approach which, combined with low-rank factorized solution, can handle large input models and provably leads to reduced-order models that are either smaller or exhibit better accuracy than full-frequency BT. © 2019 IEEE.
URI
http://hdl.handle.net/11615/71613
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  • Δημοσιεύσεις σε περιοδικά, συνέδρια, κεφάλαια βιβλίων κλπ. [19735]

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