Timing errors in sta-based gate-level simulation

Abstract

In this paper, we demonstrate that conventional STA-based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because cycle cuts create local slew errors at cutpoints, and secondly because slew propagation may not be upper-bounded across multiple cut points in the same cycle. The use of an ASTA engine, which does not cut cycles, and properly bounds slews across cycles is a possible solution, which can indeed serve as an upper bound over SPICE, transistor level similations. We contrast STA and ASTA-based SDF-Annotated gate-level simulation results, with transistor level SPICE results, and demonstrate the impact of timing errors. © 2020 IEEE.