CAS-HtBase: a new database for the study of HTs at the pre-silicon stage of ASICs

Abstract

Hardware Trojan (HT) consists a chip-level viruses which aim to leak encrypted information or degrade the performance of the infected device. They are a modification to the original design of a circuit and consist of two components, trigger, and payload. The trigger is the mechanism that calls the payload under rare conditions. The payload mechanism is responsible for the type of attack the infected circuit will receive. HTs can be inserted into any phase of the Application-Specific Integrated Circuits (ASICs) production chain. They can stay stealthy and be undetected. HTs viruses are a crucial issue in the field of electronics, with the potential to become an outbreak in the next years. A major problem is that, at the academic and research level, there is a general lack of data, a lack of uninfected benchmark circuits, a lack of the small type of uninfected and infected circuits, and a large imbalance in the amount of data between uninfected and infected circuits. We used and designed these limited benchmark circuits for the Gate Level Netlist (GLN) phase with a professional tool and extracted area, power, and time analysis features. Through these features, we created a synthetic data creation tool known as GAINESIS through which we created our CAS-HtBase. CAS-HtBase aims to provide the researchers with a new HT database based on GLN analysis exclusively for ASICs. The format of CAS-HtBase allows the development of Machine Learning (ML) models without conversions to the database. © 2022 IEEE.