RADPlace-MS: A Timing-Driven Placer and Optimiser for ASICs Radiation Hardening

Abstract

The manufacturing of modern Integrated Circuits (ICs), resistant against faults caused by ionising radiation, has become quite challenging due to the rapid advancement of VLSI technology. Additionally, the Radiation Hardening process, which involves making electronic cells and circuits resistant to damage or faults induced by ionising radiation, deviates from the conventional design flow. Thus, it generally suffers from insufficient support from industrial EDA tools. RADPlace is an academic timing-driven detailed placement algorithm that ensures spacing constraints among TMR triplet members. However, RADPlace, considering only the top critical paths of the circuit, limits the improvement in circuit timing, especially Total Negative Slack (TNS). In this work, we propose an improved RADPlace version (RADPlace-I) and a Multi-Step RADPlace version (RADPlace-MS), separating timing-driven optimisations from the placement step. Experimental results indicate that RADPlace-I achieves an average 21% improvement in Worst Negative Slack (WNS), while it achieves TNS improvement in most cases. On the other hand, RADPlace-MS achieves an average 54% and 45% improvement in WNS and TNS, respectively, compared to the original RADPlace version, with negligible impact on circuit total area and power. © 2022 IEEE.