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dc.creatorFloros G., Evmorfonoulos N., Stamoulis G.en
dc.date.accessioned2023-01-31T07:38:07Z
dc.date.available2023-01-31T07:38:07Z
dc.date.issued2019
dc.identifier10.1109/SMACD.2019.8795231
dc.identifier.isbn9781728112015
dc.identifier.urihttp://hdl.handle.net/11615/71613
dc.description.abstractModel Order Reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on Balanced Truncation (BT) offer very good error estimates and can provide compact models with any desired accuracy over the whole range of frequencies (from DC to infinity). However, in most applications the circuit is only intended to operate at specific frequency windows, which means that the reduced-order model can become unnecessarily large to achieve approximation over all frequencies. In this paper, we present a frequency-limited approach which, combined with low-rank factorized solution, can handle large input models and provably leads to reduced-order models that are either smaller or exhibit better accuracy than full-frequency BT. © 2019 IEEE.en
dc.language.isoenen
dc.sourceSMACD 2019 - 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, Proceedingsen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85071583245&doi=10.1109%2fSMACD.2019.8795231&partnerID=40&md5=51252a7fd0d3a70aa485bae7bff61c23
dc.subjectIntegrated circuit manufactureen
dc.subjectTiming circuitsen
dc.subjectBalanced truncationen
dc.subjectCircuit reductionen
dc.subjectEfficient simulationen
dc.subjectError estimatesen
dc.subjectFrequency windowsen
dc.subjectModel order reductionen
dc.subjectReduced order modelsen
dc.subjectSpecific frequenciesen
dc.subjectCircuit simulationen
dc.subjectInstitute of Electrical and Electronics Engineers Inc.en
dc.titleEfficient Circuit Reduction in Limited Frequency Windowsen
dc.typeconferenceItemen


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