A design flow for the precise identification of the worst-case voltage drop in power grid analyses
Modern IC designs contain hundreds of millions of transistors and new implementations of multi core chips take place in commercial products. Identifying worst-case voltage drop conditions in every hierarchical module supplied by the power grid is a crucial reliability problem in modern IC design. In this paper we focused our efforts on a complete design flow based on innovative results from recent research work. This approach demonstrates a new implementation of construction of the current space which is performed via plain simulation and statistical extrapolation using results from extreme value theory. Experimental results verify the potential of the estimation engine within an industrial EDA flow for performing power grid verification using a custom hierarchical design. © 2008 IEEE.
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