Listar por tema "Reconfigurable hardware"
Mostrando ítems 1-20 de 24
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Asynchronous sub-threshold ultra-low power processor
(2015)Ultra low power VLSI circuits may enable applications such as medical implants, sensor networks and things for IoT. Aggressive supply voltage scaling is known to significantly improve power consumption and efficiency, but ... -
Compiler transformations in hardware synthesis of Mpeg2 codes
(2016)High-level synthesis is the technique that translates high-level programming language programs into equivalent hardware descriptions. The use of conventional programming languages as input to high-level synthesis is ... -
Design of Reconfigurable Fault-Tolerant Datapaths
(2020)In this paper, behavioral-level synthesis techniques are presented for the design of reconfigurable hardware. The techniques are applicable for synthesis of several classes of designs, such as design for fault-tolerance ... -
The effect of teaching electric circuits switching from real to virtual lab or vice versa - A case study with junior high-school learners
(2015)The present study focuses on real and virtual labs used in unison to teach Physics. Should students be exposed to real experiments first and virtual labs afterwards, or could it be that the reverse is the best educational ... -
Efficient solution of large sparse linear systems in modern hardware
(2016)The solution of large-scale sparse linear systems arises in numerous scientific and engineering problems. Typical examples involve study of many real world multi-physics problems and the analysis of electric power systems. ... -
The experimental model of a non-ideal memristor
(2016)In this paper, the experimental study and the related evaluation of the memristive behavior demonstrated by a simple device, a tungsten filament bulb, is presented. It was found that this device operates as a non-ideal ... -
Hardware synthesis of high-level C constructs
(2015)In this paper, experiments with a useable C frontend for the CCC behavioural synthesis tools are presented and analysed. This tool combination is able to rapidly deliver provably-correct hardware implementations at the RTL ... -
High speed binary counter based on 1D Cellular Automata
(2016)This work presents a binary counter that was derived using the bASIC theory of 1D Cellular Automata. One of the 1D Cellular Automata seeds is producing an evolutionary structure in which the sequence of binary numbers is ... -
Implementation and performance comparison of the motion compensation kernel of the AVS video decoder on FPGA, GPU and multicore processors
(2011)Next generation video standards have strict and increasing performance demands due to real-time requirements and the trend towards higher frame resolutions and bit rates. Leveraging the advantages of reconfigurable logic ... -
An intelligent, uncertainty driven aggregation scheme for streams of ordered sets
(2016)Data streams management has attracted the attention of many researchers during the recent years. The reason is that numerous devices generate huge amounts of data demanding an efficient processing scheme for delivering ... -
Low power monolithic 3D IC design of asynchronous AES core
(2015)In this paper, we demonstrate, for the first time, that a monolithic 3D implementation of an asynchronous AES encryption core can achieve up to 50.3% footprint reduction, 25.7% improvement in power, 34.3% shorter wirelength ... -
Massively parallel programming models used as hardware description languages: The OpenCL case
(2011)The problem of automatically generating hardware modules from high level application representations has been at the forefront of EDA research during the last few years. In this paper, we introduce a methodology to ... -
Multithreading on reconfigurable hardware: A performance evaluation approach of a multicore FPGA architecture
(2021)This paper addresses the performance issues of multiple threads running on a multithreaded field programmable gate array (FPGA) multicore architecture, supported by a realtime variant of Linux operating system. The objective ... -
On formulating and tackling Integrated circuit placement as a scheduling problem
(2015)Integrated circuit (IC) placement consists of placing the cells of the IC on a chip plane so that overall performance is optimized. Various performance criteria have been considered with the most common being wire length. ... -
On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision
(2016)Computing systems servers-low-or high-end ones have been traditionally designed and built using a main-board and its hardware components as a 'hard' monolithic building block; this formed the base unit on which the system ... -
On the characterization of OpenCL dwarfs on fixed and reconfigurable platforms
(2014)The proliferation of heterogeneous computing platforms presents the parallel computing community with new challenges. One such challenge entails evaluating the efficacy of such parallel architectures and identifying the ... -
OpenDwarfs: Characterization of Dwarf-Based Benchmarks on Fixed and Reconfigurable Architectures
(2016)The proliferation of heterogeneous computing platforms presents the parallel computing community with new challenges. One such challenge entails evaluating the efficacy of such parallel architectures and identifying the ... -
A performance enhancement approach based on tweak process scheduling for a P1619 core
(2016)The IEEE P1619 standard was developed to protect data in shared storage media. Most of the works that have been presented until now have adopted a no robust scheduling scheme to implement various architectures. At first, ... -
SER analysis of multiple transient faults in combinational logic
(2016)In the VLSI field, reliability of chips is a major issue and it becomes more significant considering the continuous technology down-scaling. Modern chips are extremely sensitive to various factors such as radiation and, ... -
SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems on Chip
(2016)Recent advances in FPGA technology and the proliferation of High Level Synthesis (HLS) tools makes it possible to implement complex System on Chip (SoC) designs that realize complete applications in a single FPGA device. ...