A performance enhancement approach based on tweak process scheduling for a P1619 core

Abstract

The IEEE P1619 standard was developed to protect data in shared storage media. Most of the works that have been presented until now have adopted a no robust scheduling scheme to implement various architectures. At first, an exploration on P1619 applicability is being made and then a different scheduling approach, compared to the typical one which exists in literature, is being proposed. The architectures that have been implemented adopt two autonomous AES cores and have been designed properly for efficient FPGAs implementations. The contribution of the paper is the presentation of a novel scheduling scheme that allows selection of the appropriate core configuration, saving significantly in terms of cost and area requirements. © 2016 IEEE.