Πλοήγηση ανά Θέμα "Program processors"
Αποτελέσματα 1-20 από 35
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A 3-D Fast transform-based preconditioner for large-scale power grid analysis on massively parallel architectures
(2014)Efficient analysis of on-chip power delivery networks is one of the most challenging problems that EDA is confronted with. This paper addresses the problem of simulating general multi-layer power delivery networks with ... -
AcHEe: Evaluating approximate computing and heterogeneity for energy efficiency
(2018)Energy efficiency is lately a major concern for computer engineers, at the levels of both software and hardware. A popular path is the exploitation of heterogeneity and accelerator-based systems, which combine different ... -
Asynchronous sub-threshold ultra-low power processor
(2015)Ultra low power VLSI circuits may enable applications such as medical implants, sensor networks and things for IoT. Aggressive supply voltage scaling is known to significantly improve power consumption and efficiency, but ... -
Automating data management in heterogeneous systems using polyhedral analysis
(2015)In this paper we introduce a framework which automates the task of data management for OpenCL programs across multiple devices of a heterogeneous system. Our approach uses compile-time analysis, based on the polyhedral ... -
Bayesian uncertainty quantification and propagation in molecular dynamics simulations
(2012)A comprehensive Bayesian probabilistic framework is developed for quantifying and calibrating the uncertainties in the parameters of the models (e.g. force-field potentials) involved in molecular dynamics (MD) simulations ... -
Computer Vision and Pattern Recognition for the Analysis of 2D/3D Remote Sensing Data in Geoscience: A Survey
(2022)Historically, geoscience has been a prominent domain for applications of computer vision and pattern recognition. The numerous challenges associated with geoscience-related imaging data, which include poor imaging quality, ... -
CPU provisioning algorithms for service differentiation in cloud-based environments
(2015)This work focuses on the design, analysis and evaluation of Dynamic Weighted Round Robin (DWRR) algorithms that can guarantee CPU service shares in clusters of servers. Our motivation comes from the need to provision ... -
Dynamic Undervolting to Improve Energy Efficiency on Multicore X86 CPUs
(2020)Chip manufacturers introduce redundancy at various levels of CPU design to guarantee correct operation, even for worst-case combinations of non-idealities in process variation and system operating conditions. This redundancy ... -
Efficient exploitation of parallel computing on the server-side of health organizations' intranet for distributing medical images to smart devices
(2012)The distribution of high-resolution medical images to smart devices, in a health organization premises, is considered in this work. The aim is to reduce network traffic and computation load (of the smart devices). Security ... -
Efficient solution of large sparse linear systems in modern hardware
(2016)The solution of large-scale sparse linear systems arises in numerous scientific and engineering problems. Typical examples involve study of many real world multi-physics problems and the analysis of electric power systems. ... -
Efficient techniques for bayesian inverse modeling of large-order computational models
(2013)Bayesian tools for inverse modeling are based on asymptotic approximations and Stochastic Simulation Algorithms (SSA). Such tools require a number of moderate to large number of system re-analyses. For large-order numerical ... -
Enhancing design space exploration by extending CPU/GPU specifications onto FPGAs
(2015)The design cycle for complex special-purpose computing systems is extremely costly and time-consuming. It involves a multiparametric design space exploration for optimization, followed by design verification. Designers of ... -
Exploiting CPU voltage margins to increase the profit of cloud infrastructure providers
(2019)Energy efficiency is a major concern for cloud computing, with CPUs accounting a significant fraction of datacenter nodes power consumption. CPU manufacturers introduce voltage margins to guarantee correct operation. ... -
Extracting coarse-grained pipelined parallelism out of sequential applications for parallel processor arrays
(2009)We present development and runtime support for building application specific data processing pipelines out of sequential code, and for executing them on a general purpose platform that features a reconfigurable Parallel ... -
Fast computing techniques for Bayesian uncertainty quantification in structural dynamics
(2013)A Bayesian probabilistic framework for uncertainty quantification and propagation in structural dynamics is reviewed. Fast computing techniques are integrated with the Bayesian framework to efficiently handle large-order ... -
Fast Transform-based preconditioners for large-scale power grid analysis on massively parallel architectures
(2012)Efficient analysis of massive on-chip power delivery networks is among the most challenging problems facing the EDA industry today. In this paper, we present a new preconditioned iterative method for fast DC and transient ... -
A framework for evaluating software on reduced margins hardware
(2018)To improve power efficiency, researchers are experimenting with dynamically adjusting the voltage and frequency margins of systems to just above the minimum required for reliable operation. Traditionally, manufacturers did ... -
GPU-Based Algorithms for Processing the k Nearest-Neighbor Query on Disk-Resident Data
(2021)Algorithms for answering the k Nearest-Neighbor (k-NN) query are widely used for queries in spatial databases and for distance classification of a group of query points against a reference dataset to derive the dominating ... -
The Impact of CPU Voltage Margins on Power-Constrained Execution
(2022)CPUs typically operate at a voltage which is higher than what is strictly required, using voltage margins to account for process variability and anticipate any combination of adverse operating conditions. However, these ... -
Implementation and performance analysis of SEAL encryption on FPGA, GPU and multi-core processors
(2011)Accelerators, such as field programmable gate arrays (FPGAs) and graphics processing units (GPUs), are special purpose processors designed to speed up compute-intensive sections of applications. FPGAs are highly customizable, ...