Πλοήγηση ανά Θέμα "Quality loss"
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Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios
(2022)Standard-cell placement is the fundamental step in a typical VLSI/ASIC design flow. Its result, paired with the outcome of the routing procedure can be the decisive factor in rendering a design manufacturable. Global ... -
Variations on a Connectivity-based Legalizer for Standard Cell Design
(2021)Legalization is considered the most significant step in a placement correlated standard cell design flow as moving cells towards legal positions to avoid overlap among them may escalate the overall wire length. Monolithic ...