Instruction-Flow-Based Timing Analysis in Pipelined Processors

Abstract

Microprocessor design utilizes timing analysis in order to establish the maximal operation clock speed of the circuit. In static timing analysis, clock frequency is set in accord with the worst-case delay in the circuit operation, regardless of the possible circuit inputs. Dynamic timing analysis approaches consider variations in the inputs, obtaining more accurate values for the clock speed. However, such methodologies are in general very slow. Recent research on static timing analysis is focused on better-than-worst-case algorithms, which attempt to introduce a dynamic flavor to the static approach. The work presented in this paper is concentrated on a certain aspect of better-than-worst-case timing analysis for processor design, obtaining a more optimistic clock speed than the one produced by pure static analysis. Certain variations of the inputs to the processor circuit are considered, in order to overcome the limitations of traditional techniques and increase clock frequency. In particular, given that the circuit inputs are mostly instructions of the processor instruction set, we have chosen to vary the instruction opcode of the input set. Thus, we have designed and implemented an algorithm, which produces timing information for each instruction and for each possible flow between consecutive instructions in the pipeline. In such a way, the designer is able to focus on improving the architecture of particular instructions rather than redesigning circuit parts. We have tested our algorithm on an OpenRISC processor design and collected timing information through an innovative use of the Synopsis PrimeTime tool. A comparison against timing information obtained through traditional static timing analysis proves that our algorithm succeeds to give better-than-worst-case timing for the most common instructions. Finally, the timing obtained through considering instruction flow and not static instructions, is more accurate and is thus more useful for the designer to deliver a better product. © 2019 IEEE.