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Wafer Map Defect Pattern Recognition using Imbalanced Datasets
dc.creator | Tziolas T., Theodosiou T., Papageorgiou K., Rapti A., Dimitriou N., Tzovaras D., Papageorgiou E. | en |
dc.date.accessioned | 2023-01-31T10:22:22Z | |
dc.date.available | 2023-01-31T10:22:22Z | |
dc.date.issued | 2022 | |
dc.identifier | 10.1109/IISA56318.2022.9904402 | |
dc.identifier.isbn | 9781665463904 | |
dc.identifier.uri | http://hdl.handle.net/11615/80265 | |
dc.description.abstract | The accurate and automatic inspection of wafer maps is vital for semiconductor engineers to identify defect causes and to optimize the wafer fabrication process. This research work seeks to address the pattern recognition task for the identification of defects in wafer maps, by developing a deep Convolutional Neural Network (CNN) classifier. The proposed CNN-based model utilizes various pre- and post-processing tools and is applied on the public but highly imbalanced industrial dataset WM-811K. To handle imbalance, a methodology of treating each class individually is proposed by applying different processing techniques for down-sampling, splitting and data augmentation based on the number of samples. The proposed model achieves 95.3% accuracy and 93.78% macro F1-score and outperformes other models in the related literature concerning the identification of the majority of classes. © 2022 IEEE. | en |
dc.language.iso | en | en |
dc.source | 13th International Conference on Information, Intelligence, Systems and Applications, IISA 2022 | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85141033460&doi=10.1109%2fIISA56318.2022.9904402&partnerID=40&md5=48b75c2d7867a3970d92c9eb49373f36 | |
dc.subject | Classification (of information) | en |
dc.subject | Convolution | en |
dc.subject | Deep neural networks | en |
dc.subject | Defects | en |
dc.subject | Pattern recognition | en |
dc.subject | Semiconductor device manufacture | en |
dc.subject | Silicon wafers | en |
dc.subject | Automatic inspection | en |
dc.subject | Convolutional neural network | en |
dc.subject | Defect patterns | en |
dc.subject | Fabrication process | en |
dc.subject | Imbalance processing | en |
dc.subject | Imbalanced dataset | en |
dc.subject | Semiconductor industry | en |
dc.subject | Wafer fabrications | en |
dc.subject | Wafer maps | en |
dc.subject | WM-811k | en |
dc.subject | Convolutional neural networks | en |
dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
dc.title | Wafer Map Defect Pattern Recognition using Imbalanced Datasets | en |
dc.type | conferenceItem | en |
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