| dc.creator | Souliotis G., Laoudias C., Plessas F., Terzopoulos N. | en |
| dc.date.accessioned | 2023-01-31T09:59:23Z | |
| dc.date.available | 2023-01-31T09:59:23Z | |
| dc.date.issued | 2016 | |
| dc.identifier | 10.1007/s00034-015-0082-9 | |
| dc.identifier.issn | 0278081X | |
| dc.identifier.uri | http://hdl.handle.net/11615/79219 | |
| dc.description.abstract | An analog phase interpolator with improved step linearity is presented in this paper. The linearity is improved by setting the time constant of the output nodes in suitable value and by employing a fine trimming technique. The performance and the improved linearity have been verified with post-layout simulations using a well-established CMOS 65 nm technology and transistors with standard threshold voltages. The clock frequency is at 2.5 GHz and the core voltage supply at 1.2 V. Its low phase noise makes the circuit suitable for high-speed systems where low jitter performance is required. © 2015, Springer Science+Business Media New York. | en |
| dc.language.iso | en | en |
| dc.source | Circuits, Systems, and Signal Processing | en |
| dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84961388675&doi=10.1007%2fs00034-015-0082-9&partnerID=40&md5=c5b77b9f531b56ac98699e604bc03691 | |
| dc.subject | Clocks | en |
| dc.subject | Threshold voltage | en |
| dc.subject | Analog phase interpolator | en |
| dc.subject | Clock and data recovery | en |
| dc.subject | High speed systems | en |
| dc.subject | Low-jitter performance | en |
| dc.subject | Phase interpolator | en |
| dc.subject | Post layout simulation | en |
| dc.subject | SerDes | en |
| dc.subject | Trimming techniques | en |
| dc.subject | Interpolation | en |
| dc.subject | Birkhauser Boston | en |
| dc.title | Phase Interpolator with Improved Linearity | en |
| dc.type | journalArticle | en |
