| dc.creator | Simoglou S., Xiromeritis N., Sotiriou C., Sketopoulos N. | en |
| dc.date.accessioned | 2023-01-31T09:56:15Z | |
| dc.date.available | 2023-01-31T09:56:15Z | |
| dc.date.issued | 2020 | |
| dc.identifier | 10.1016/j.vlsi.2020.05.005 | |
| dc.identifier.issn | 01679260 | |
| dc.identifier.uri | http://hdl.handle.net/11615/78989 | |
| dc.description.abstract | We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its additional requirement over STA is a graph-based Event Model, Marked Graph or Petri Net. We contrast STA, ASTA results for 23 asynchronous circuit benchmarks, and demonstrate significant timing differences between the ASTA critical cycle and STA critical path, with cut cycles. We also demonstrate our correlation to SPICE level simulations, for 20 of the 23 circuits. Our ASTA flow effectively upper bounds critical cycle delay over SPICE, and is orders of magnitude faster. © 2020 Elsevier B.V. | en |
| dc.language.iso | en | en |
| dc.source | Integration | en |
| dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85088108011&doi=10.1016%2fj.vlsi.2020.05.005&partnerID=40&md5=6319058dbfa551db87be07a06f56fc79 | |
| dc.subject | Graphic methods | en |
| dc.subject | Petri nets | en |
| dc.subject | Timing circuits | en |
| dc.subject | Asynchronous circuits | en |
| dc.subject | Asynchronous control circuits | en |
| dc.subject | Asynchronous controllers | en |
| dc.subject | Critical Paths | en |
| dc.subject | Marked graphs | en |
| dc.subject | Orders of magnitude | en |
| dc.subject | Static timing analysis | en |
| dc.subject | Upper Bound | en |
| dc.subject | SPICE | en |
| dc.subject | Elsevier B.V. | en |
| dc.title | Graph-based STA for asynchronous controllers | en |
| dc.type | journalArticle | en |
