| dc.description.abstract | In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology uses Graph-based Analysis (GBA) STA principles, is fast, is able to compute setup or hold slacks on sequential elements, and operates without cycle cutting. Industrial Timing Libraries, Verilog input and multiple PVT corners are supported. To perform STA on the cyclic circuit portion, a Graph-based Event Model, a live and 1-bounded Signal Transition Graph (STG), i.e. a simplified PeTri-Net (PTnet), the Event Timing Graph (ETG), is automatically generated from the netlist and the associated timing arcs. The ETG is a cyclic, timing arcs graph, the period analysis of which can identify the cyclic portion's period and Critical Cycle(s). The acyclic portion's STA may be subsequently performed, based on the cyclic portion's Arrival Times (AT). We illustrate an algorithm for automated ETG construction, based solely on circuit components, and their technology library (.lib) timing arcs unateness. We prove that the generated ETG will be live and 1-bounded. Our STA approach is demonstrated on three practical, mixed cyclic, acyclic circuits, a ring-oscillator, a Vernier delay line, and a GALS controller. © 2020 IEEE. | en |
