A High-Performance Neuron for Artificial Neural Network based on Izhikevich model

Abstract

Neuromorphic circuits have gained a lot of interest through the last decades since they may be deployed in a large spectrum of scientific research. In this paper a hardware realization of a single neuron targeting Field Programmable Gate Arrays (FPGA) with 6 levels of pipeline is presented. The proposed circuit implements the Izhikevich's model and is presenting better performance compared to a previous pipelined design. The proposed implementation is based on fixed-point arithmetic, allowing faster computations on values related to the membrane potential and the membrane recovery variable of the neuron. The exploitation of balanced and reduced stages of pipeline, in combination to the fixed point arithmetic, offers two significant characteristics. The circuits characteristics are higher performance up to 14%, achieving also parallel computation, better simulation of the actual operation of a neuron, while area requirements of the FPGA implementation remain low as the initial reference design. The proposed circuit is the first of its kind, in an effort to minimize area and at the same time improve performance of an artificial neuron. © 2019 IEEE.