Mostra i principali dati dell'item
Low power monolithic 3D IC design of asynchronous AES core
dc.creator | Penmetsa N.L., Sotiriou C., Lim S.K. | en |
dc.date.accessioned | 2023-01-31T09:47:01Z | |
dc.date.available | 2023-01-31T09:47:01Z | |
dc.date.issued | 2015 | |
dc.identifier | 10.1109/ASYNC.2015.22 | |
dc.identifier.isbn | 9781479987153 | |
dc.identifier.issn | 15228681 | |
dc.identifier.uri | http://hdl.handle.net/11615/78038 | |
dc.description.abstract | In this paper, we demonstrate, for the first time, that a monolithic 3D implementation of an asynchronous AES encryption core can achieve up to 50.3% footprint reduction, 25.7% improvement in power, 34.3% shorter wirelength and 6.06% reduced cell area compared to its 2D counterpart, at identical (ISO) performance. We also demonstrate that combining asynchronous circuits with 3D integration can yield a peak power reduction of 63.9% compared to the equivalent synchronous realisation. We also verified that the asynchronous implementation of the encryption core is more tolerant to monolithic 3D tier-tier variation compared to its synchronous counterpart. To the best of our knowledge, this is the first paper to discuss the mutual benefits of asynchronous and monolithic 3D IC integration. © 2015 IEEE. | en |
dc.language.iso | en | en |
dc.source | Proceedings - International Symposium on Asynchronous Circuits and Systems | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84962606465&doi=10.1109%2fASYNC.2015.22&partnerID=40&md5=9690ceb334f231bc7b9b60ba2bef206d | |
dc.subject | Asynchronous sequential logic | en |
dc.subject | Cryptography | en |
dc.subject | Equivalent circuits | en |
dc.subject | Reconfigurable hardware | en |
dc.subject | Three dimensional integrated circuits | en |
dc.subject | 3-D integration | en |
dc.subject | 3D IC design | en |
dc.subject | AES encryption | en |
dc.subject | Asynchronous circuits | en |
dc.subject | Low Power | en |
dc.subject | Mutual benefit | en |
dc.subject | Peak power reduction | en |
dc.subject | Wire length | en |
dc.subject | Integrated circuit design | en |
dc.subject | IEEE Computer Society | en |
dc.title | Low power monolithic 3D IC design of asynchronous AES core | en |
dc.type | conferenceItem | en |
Files in questo item
Files | Dimensione | Formato | Mostra |
---|---|---|---|
Nessun files in questo item. |