Low power monolithic 3D IC design of asynchronous AES core

Abstract

In this paper, we demonstrate, for the first time, that a monolithic 3D implementation of an asynchronous AES encryption core can achieve up to 50.3% footprint reduction, 25.7% improvement in power, 34.3% shorter wirelength and 6.06% reduced cell area compared to its 2D counterpart, at identical (ISO) performance. We also demonstrate that combining asynchronous circuits with 3D integration can yield a peak power reduction of 63.9% compared to the equivalent synchronous realisation. We also verified that the asynchronous implementation of the encryption core is more tolerant to monolithic 3D tier-tier variation compared to its synchronous counterpart. To the best of our knowledge, this is the first paper to discuss the mutual benefits of asynchronous and monolithic 3D IC integration. © 2015 IEEE.