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  •   University of Thessaly Institutional Repository
  • Επιστημονικές Δημοσιεύσεις Μελών ΠΘ (ΕΔΠΘ)
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  •   University of Thessaly Institutional Repository
  • Επιστημονικές Δημοσιεύσεις Μελών ΠΘ (ΕΔΠΘ)
  • Δημοσιεύσεις σε περιοδικά, συνέδρια, κεφάλαια βιβλίων κλπ.
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Machine Learning for Hardware Trojan Detection: A Review

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Author
Liakos K.G., Georgakilas G.K., Moustakidis S., Karlsson P., Plessas F.C.
Date
2019
Language
en
DOI
10.1109/PACET48583.2019.8956251
Keyword
Error detection
Hardware security
Integrated circuits
Learning systems
Malware
Reverse engineering
Viruses
Classification approach
Encrypted informations
Engineering development
Hardware Trojan detection
Integrated circuits (ICs)
Literature reviews
Machine learning methods
prevention
Machine learning
Institute of Electrical and Electronics Engineers Inc.
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Abstract
Every year, the rate at which technology is applied on areas of our everyday life is increasing at a steady pace. This rapid development drives the technology companies to design and fabricate their integrated circuits (ICs) in non-trustworthy outsourcing foundries in order to reduce the cost. Thus, a synchronous form of virus, known as Hardware Trojans (HTs), was developed. HTs leak encrypted information, degrade device performance or lead to total destruction. To reduce the risks associated with these viruses, various approaches have been developed aiming to prevent and detect them, based on conventional or machine learning methods. Ideally, any undesired modification made to an IC should be detectable by pre-silicon verification/simulation and post-silicon testing. The infected circuit can be inserted in different stages of the manufacturing process, rendering the detection of HTs a complicated procedure. In this paper, we present a comprehensive review of research dedicated to applications based on Machine Learning for the detection of HTs in ICs. The literature is categorized in (a) reverse-engineering development for the imaging phase, (b) real-time detection, (c) golden model-free approaches, (d) detection based on gate-level netlists features and (e) classification approaches. © 2019 IEEE.
URI
http://hdl.handle.net/11615/75812
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  • Δημοσιεύσεις σε περιοδικά, συνέδρια, κεφάλαια βιβλίων κλπ. [19735]
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