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Exploiting CPU voltage margins to increase the profit of cloud infrastructure providers

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Auteur
Kalogirou C., Koutsovasilis P., Antonopoulos C.D., Bellas N., Lalis S., Venugopal S., Pinto C.
Date
2019
Language
en
DOI
10.1109/CCGRID.2019.00044
Sujet
Cluster computing
Cost effectiveness
Cost reduction
Dynamic frequency scaling
Electric power utilization
Energy efficiency
Energy utilization
Grid computing
Program processors
Reduction
Scheduling
Voltage scaling
Cloud infrastructures
Dynamic voltage frequency scaling
Extended margins
Modeling and scheduling
Performance degradation
Service Level Agreements
Undervolting
Workload consolidation
Green computing
Institute of Electrical and Electronics Engineers Inc.
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Résumé
Energy efficiency is a major concern for cloud computing, with CPUs accounting a significant fraction of datacenter nodes power consumption. CPU manufacturers introduce voltage margins to guarantee correct operation. However, these are unnecessarily wide for real-world execution scenarios, and translate to increased power consumption. In this paper, we investigate how such margins can be exploited by infrastructure operators, by selectively undervolting nodes, at the controlled risk of inducing failures and activating service-level agreement (SLA) violation penalties. We model the problem in a formal way, capturing the most important aspects that drive VM management and system configuration decisions. Then, we introduce XM-VFS policy that reduces infrastructure operator costs by reducing voltage margins, and compare it with the state-of-the-art which employs dynamic voltage-frequency scaling (DVFS) and workload consolidation. We perform simulations to quantify the cost reduction, considering the energy consumption and potential SLA violations. Our results show significant gains, up to 17.35% and 16.32% for the energy and cost reduction respectively. In our simulations, we use realistic assumptions for voltage margins, energy consumption and performance degradation of applications due to frequency scaling, based on the characterization of commercial Intel-and ARM-based machines. Our model and scheduling policy are generic and scalable. © 2019 IEEE.
URI
http://hdl.handle.net/11615/74204
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