Loop pipelining in high-level synthesis with CCC

Abstract

High-level synthesis allows the use of high-level programming languages for hardware design. Traditional programming with the C and ADA languages can lead to efficient hardware description through recently developed high-level synthesis tools. Compilers play an important role in this process, since they can bridge differences between software programming and hardware design methodologies, thus making high-level synthesis tools better accepted by the scientific community. Furthermore, modern compiler optimizations can be employed in order to obtain optimal hardware descriptions. Loop transformations are often the focus of compiler optimizations, since they can result in significant performance improvement, for both software and hardware programming. In this paper, we discuss the implementation of loop pipelining in the front-end compiler of the CCC high-level synthesis tool, and in particular we present new optimization techniques that lead to a decreased number of states in the FSM-based output of CCC. We present several experiments conducted on the Livermore loops and the MPEG2 open-source code, which prove the claimed improvement. © 2017 IEEE.