Εμφάνιση απλής εγγραφής

dc.creatorDimitriou G., Dossis M., Stamoulis G.en
dc.date.accessioned2023-01-31T07:56:14Z
dc.date.available2023-01-31T07:56:14Z
dc.date.issued2018
dc.identifier10.23919/SEEDA-CECNSM.2018.8544930
dc.identifier.isbn9786188331419
dc.identifier.urihttp://hdl.handle.net/11615/73335
dc.description.abstractResearch and industry interest in high-level synthesis has been renewed in the last few years, proven by the introduction of new tools or improved versions of existing tools. Academic tools like Gaut or CCC have recently appeared in new versions with expanded functionality in order to cover increased hardware design requirements. Likewise, industrial tools like Xilinx VivadoHLS or, more recently, Cadence Stratus have appeared and are continuously evolving in their effort to succeed in the market. One technology that high-level synthesis tools have chosen to invest on is compiler-driven code optimizations, which are a promising means to improve efficiency of automatically generated hardware. Loop transformations are among the most popular compiler optimizations, for both software and hardware targets. Loop unrolling and loop pipelining, coupled with careful instruction reordering, can deliver highly optimized output. Instruction dependencies play a significant role in such optimizations, limiting performance improvement for the final code. In this paper, we discuss the issue of dependencies among loop body operations, especially those forming cycles, and their impact on high-level synthesis. We present results from experiments with several benchmarks on the CCC and VivadoHLS tools, showing that CCC can deliver better output than VivadoHLS in the presence of complex operation dependence cycles. © 2018 Tei of Western Macedonia.en
dc.language.isoenen
dc.sourceSouth-East Europe Design Automation, Computer Engineering, Computer Networks and Social Media Conference, SEEDA_CECNSM 2018en
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85059770173&doi=10.23919%2fSEEDA-CECNSM.2018.8544930&partnerID=40&md5=8de7ca8c7b2ff20496f789b33c43a764
dc.subjectComputer aided designen
dc.subjectComputer hardwareen
dc.subjectComputer hardware description languagesen
dc.subjectComputer networksen
dc.subjectHigh level synthesisen
dc.subjectIndustrial researchen
dc.subjectProgram compilersen
dc.subjectSocial networking (online)en
dc.subjectAutomatically generateden
dc.subjectCompiler optimizationsen
dc.subjectHardware synthesisen
dc.subjectLimiting performanceen
dc.subjectLoop pipeliningen
dc.subjectLoop transformationen
dc.subjectRTL designsen
dc.subjectSoftware and hardwaresen
dc.subjectHigh level languagesen
dc.subjectInstitute of Electrical and Electronics Engineers Inc.en
dc.titleOperation Dependencies in Loop Pipelining for High-Level Synthesisen
dc.typeconferenceItemen


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