| dc.creator | Christakis C., Theodoridis G., Kakarountas A. | en |
| dc.date.accessioned | 2023-01-31T07:46:02Z | |
| dc.date.available | 2023-01-31T07:46:02Z | |
| dc.date.issued | 2016 | |
| dc.identifier | 10.1109/MOCAST.2016.7495170 | |
| dc.identifier.isbn | 9781467396806 | |
| dc.identifier.uri | http://hdl.handle.net/11615/72833 | |
| dc.description.abstract | This work presents a binary counter that was derived using the bASIC theory of 1D Cellular Automata. One of the 1D Cellular Automata seeds is producing an evolutionary structure in which the sequence of binary numbers is reproduced in selective bit positions. The main characteristic of this counting sequence is that it is produced with low complexity with a small penalty of information redundancy. The proposed counter was implemented in FPGA technology and it is performing better than any other binary counter reported in literature. Also, in the majority of the cases, its performance overcomes even FPGA vendor's available soft IP core. © 2016 IEEE. | en |
| dc.language.iso | en | en |
| dc.source | 2016 5th International Conference on Modern Circuits and Systems Technologies, MOCAST 2016 | en |
| dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84981306472&doi=10.1109%2fMOCAST.2016.7495170&partnerID=40&md5=3959d0d2d09bc6a74399e15c289db283 | |
| dc.subject | Cellular automata | en |
| dc.subject | Digital circuits | en |
| dc.subject | Field programmable gate arrays (FPGA) | en |
| dc.subject | Reconfigurable hardware | en |
| dc.subject | Basic theory | en |
| dc.subject | Binary counters | en |
| dc.subject | Binary number | en |
| dc.subject | FPGA technology | en |
| dc.subject | FPGA vendors | en |
| dc.subject | Information redundancies | en |
| dc.subject | performance | en |
| dc.subject | Soft IP core | en |
| dc.subject | Bins | en |
| dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
| dc.title | High speed binary counter based on 1D Cellular Automata | en |
| dc.type | conferenceItem | en |