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A rigorous approach for the sparsification of dense matrices in model order reduction of RLC circuits
dc.creator | Antoniadis C., Evmorfopoulos N., Stamoulis G. | en |
dc.date.accessioned | 2023-01-31T07:32:08Z | |
dc.date.available | 2023-01-31T07:32:08Z | |
dc.date.issued | 2019 | |
dc.identifier | 10.1145/3316781.3317751 | |
dc.identifier.isbn | 9781450367257 | |
dc.identifier.issn | 0738100X | |
dc.identifier.uri | http://hdl.handle.net/11615/70671 | |
dc.description.abstract | The integration of more components into modern Systems-on-Chip (SoCs) has led to very large RLC parasitic networks consisting of million of nodes, which have to be simulated in many times or frequencies to verify the proper operation of the chip. Model Order Reduction techniques have been employed routinely to substitute the large scale parasitic model by a model of lower order with similar response at the input/output ports. However, all established MOR techniques result in dense system matrices that render their simulation impractical. To this end, in this paper we propose a methodology for the sparsification of the dense circuit matrices resulting from Model Order Reduction of general RLC circuits, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy. © 2019 Association for Computing Machinery. | en |
dc.language.iso | en | en |
dc.source | Proceedings - Design Automation Conference | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85067805121&doi=10.1145%2f3316781.3317751&partnerID=40&md5=eb1e2e7292bb3a46ef81740e1047200d | |
dc.subject | Circuit resonance | en |
dc.subject | Circuit theory | en |
dc.subject | Computer aided design | en |
dc.subject | System-on-chip | en |
dc.subject | Timing circuits | en |
dc.subject | Diagonally dominant matrix | en |
dc.subject | Loss of accuracy | en |
dc.subject | Model order reduction | en |
dc.subject | Parasitic network | en |
dc.subject | Reduced systems | en |
dc.subject | Rigorous approach | en |
dc.subject | Sparsity ratios | en |
dc.subject | Systems on chips | en |
dc.subject | Resonant circuits | en |
dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
dc.title | A rigorous approach for the sparsification of dense matrices in model order reduction of RLC circuits | en |
dc.type | conferenceItem | en |
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