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  •   University of Thessaly Institutional Repository
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  • Επιστημονικές Δημοσιεύσεις Μελών ΠΘ (ΕΔΠΘ)
  • Δημοσιεύσεις σε περιοδικά, συνέδρια, κεφάλαια βιβλίων κλπ.
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Multithreading on reconfigurable hardware: A performance evaluation approach of a multicore FPGA architecture

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Author
Adam G.K.
Date
2021
Language
en
DOI
10.1504/IJHPSA.2021.119154
Keyword
Computer operating systems
Iterative methods
Logic gates
Memory architecture
Real time systems
Reconfigurable architectures
Reconfigurable hardware
Software architecture
Evaluation approach
Multi-cores
Multi-threading
Multithreaded
Performance
Performance measurements
Performances evaluation
Real- time
Real.time operating system
RTOS
Field programmable gate arrays (FPGA)
Inderscience Publishers
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Abstract
This paper addresses the performance issues of multiple threads running on a multithreaded field programmable gate array (FPGA) multicore architecture, supported by a realtime variant of Linux operating system. The objective is to investigate the efficiency of running in parallel and concurrently multithreaded applications and evaluate performance metrics including execution time, speedup, response latency, and CPU and memory usage. The development platform is a 16-core architecture implemented with Nios II soft processors on an ALTERA Cyclone IV FPGA. Performance is analysed and evaluated based upon the development and implementation of an iterative algorithm for the generation and execution of multithreaded tasks. Experimental tests were executed in a number of cores configurations and threads combinations under different workloads, such as matrix multiplication and read-write operations on on-chip memory. The results confirm the validity of the proposed approach in running and evaluating efficiently multithreaded tasks in real-time with noticeable performance improvements in terms of timing features. © 2021 Inderscience Enterprises Ltd.
URI
http://hdl.handle.net/11615/70259
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