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Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor
dc.creator | Koziri, M. | en |
dc.creator | Bellas, N. | en |
dc.creator | Katsavounidis, I. | en |
dc.creator | Zacharis, D. | en |
dc.date.accessioned | 2015-11-23T10:36:59Z | |
dc.date.available | 2015-11-23T10:36:59Z | |
dc.date.issued | 2010 | |
dc.identifier | 10.1109/ICCE.2010.5418696 | |
dc.identifier.isbn | 9781424443161 | |
dc.identifier.uri | http://hdl.handle.net/11615/30013 | |
dc.description.abstract | This paper presents the implementation of Advanced Audio and Video Standard Part 2: Video (AVS P2), the Chinese video standard, to Diamond 388VDO Video Processor, a heterogeneous dual core Tensilica SIMD processor. Through the process of mapping AVS video decoder to 388VDO we aim to explore and exploit the different forms of parallelism inherent in a video application in order to speedup AVS decoding and achieve real time functionality. ©2010 IEEE. | en |
dc.source.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-77950124345&partnerID=40&md5=25712b3cd0d50b004f497321441d2f89 | |
dc.subject | Audio and video | en |
dc.subject | Dual core | en |
dc.subject | Real time | en |
dc.subject | Tensilica | en |
dc.subject | Video applications | en |
dc.subject | Video decoders | en |
dc.subject | Video processor | en |
dc.subject | Video standard | en |
dc.subject | Consumer electronics | en |
dc.subject | Decoding | en |
dc.title | Implementation of the AVS video decoder on a heterogeneous dual-core SIMD processor | en |
dc.type | conferenceItem | en |
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