Mostrar el registro sencillo del ítem
Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicores
dc.creator | Georgakoudis, G. | en |
dc.creator | Nikolopoulos, D. S. | en |
dc.creator | Lalis, S. | en |
dc.date.accessioned | 2015-11-23T10:27:31Z | |
dc.date.available | 2015-11-23T10:27:31Z | |
dc.date.issued | 2013 | |
dc.identifier | 10.1145/2446920.2446924 | |
dc.identifier.isbn | 9781450319713 | |
dc.identifier.uri | http://hdl.handle.net/11615/27730 | |
dc.description.abstract | Asymmetric multicore processors have demonstrated a strong potential for improving performance and energy-efficiency. Shared-ISA asymmetric multicore processors overcome pro- grammability problems in disjoint-ISA systems and enhance single-ISA architectures with instruction based asymmetry. In such a design, processors share a common, baseline ISA and performance enhanced (PE) cores extend the baseline ISA with instructions that accelerate performance-critical operations. To exploit asymmetry, the scheduler should be able to migrate threads based on their acceleration potential. The contribution of this paper is a low overhead binary code rewriting method for shared-ISA multicore processors that transforms a binary executable at runtime, according to the scheduled processor's PE capabilities. The mutable binary code can be re-targeted among heterogeneous cores at any point in execution while preserving functional equivalence and using PE instructions, transparently, when avail- able, thus enabling migrations among heterogeneous cores. We emulate a realistic shared-ISA asymmetric multicore system using actual hardware { an FPGA experimental prototype. Experimental analysis shows that dynamic binary rewriting is feasible with little overhead. Rewritten code speeds up successfully baseline code while performing close, with 70% average efficiency, to non-portable, compiler generated code, statically optimized to use PE instructions. Copyright 2013 ACM. | en |
dc.source.uri | http://www.scopus.com/inward/record.url?eid=2-s2.0-84875469301&partnerID=40&md5=2176d633540df5149c32f06fd123f6bf | |
dc.subject | Binary rewriting | en |
dc.subject | Code optimization | en |
dc.subject | Heterogeneous multicore | en |
dc.subject | Shared asymmetric isa | en |
dc.subject | Compiler-generated codes | en |
dc.subject | Experimental prototype | en |
dc.subject | Functional equivalence | en |
dc.subject | Improving performance | en |
dc.subject | Binary codes | en |
dc.subject | Network components | en |
dc.subject | Optimization | en |
dc.subject | Program compilers | en |
dc.subject | Computer architecture | en |
dc.title | Fast dynamic binary rewriting to support thread migration in shared-ISA asymmetric multicores | en |
dc.type | conferenceItem | en |
Ficheros en el ítem
Ficheros | Tamaño | Formato | Ver |
---|---|---|---|
No hay ficheros asociados a este ítem. |