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dc.creatorDimitropulos, P. D.en
dc.creatorNikolaidis, S. P.en
dc.creatorKarampatzakis, D. P.en
dc.creatorStamoulis, G. I.en
dc.date.accessioned2015-11-23T10:25:40Z
dc.date.available2015-11-23T10:25:40Z
dc.date.issued2004
dc.identifier.urihttp://hdl.handle.net/11615/27097
dc.description.abstractCapacitive sensor manufacturing processes are rarely compatible with CMOS technologies and, thus, monolithic integration of sensing device and signal-conditioning IC is often not possible. Multi-chip packaging and wire bonding in employed instead, to interconnect sensor and IC dies. In such cases, sensor capacitance is comparable or even smaller than the parasitic interconnection capacitance, while interconnection parasitic resistance inserts additional signal distortion. The signal-conditioning IC must be designed to compensate for these parasitic effects. Switched-Capacitor IC's may fulfil such specifications but the use of several operational amplifiers and intricate clocking schemes increase design complexity, die-size, and power consumption, which is inappropriate for wireless applications. In this work a low-power Switched-Capacitor IC for sub-fF capacitance measurements is presented. The proposed design requires two non-overlapping clocks but no operational amplifiers. It shows excellent robustness against interconnection parasitics, transistor dimensional mismatches, temperature, and process variations. © 2004 IEEE.en
dc.source.urihttp://www.scopus.com/inward/record.url?eid=2-s2.0-27944498977&partnerID=40&md5=9f115dd5d4aacc6a01fa14081211b57c
dc.subjectCapacitanceen
dc.subjectCMOS integrated circuitsen
dc.subjectIntegrationen
dc.subjectOptical interconnectsen
dc.subjectRobustness (control systems)en
dc.subjectSignal processingen
dc.subjectVLSI circuitsen
dc.subjectCapacitive sensorsen
dc.subjectClocking schemesen
dc.subjectInterconnect sensorsen
dc.subjectParasitic effectsen
dc.subjectSensorsen
dc.titleA low-power CMOS VLSI circuit for signal conditioning in integrated capacitive sensorsen
dc.typeconferenceItemen


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