Now showing items 1-3 of 3

    • A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration and slew rate control 

      Plessas, F.; Davrazos, E.; Alexandropoulos, A.; Birbas, M.; Kikidis, J. (2012)
      A 1 GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driven has been developed for the first time to our knowledge using a 90 nm CMOS process. To satisfy the signal integrity requirements the ...
    • A 1 V CMOS programmable accurate charge pump with wide output voltage range 

      Tsitouras, A.; Plessas, F.; Birbas, M.; Kalivas, G. (2011)
      A 1 V, programmable, accurate, high speed, single-ended charge pump is proposed, suitable for low voltage PLLs. It is designed in TSMC 90-nm digital CMOS process and it consists of four switches in a current steering ...
    • A sub-1V supply CMOS voltage reference generator 

      Tsitouras, A.; Plessas, F.; Birbas, M.; Kikidis, J.; Kalivas, G. (2012)
      An integrated sub-1V voltage reference generator, designed in standard 90-nm CMOS technology, is presented in this paper. The proposed voltage reference circuit consists of a conventional bandgap core based on the use of ...