Πλοήγηση ανά Θέμα "Static timing analysis"

Accurate Estimation of Dynamic Timing Slacks using Event-Driven Simulation

Garyfallou D., Tsiokanos I., Evmorfopoulos N., Stamoulis G., Karakonstantis G. (2020)

The pessimistic nature of conventional static timing analysis has turned the attention of many studies to the exploitation of the dynamic data-dependent excitation of paths. Such studies may have revealed extensive dynamic ...

EVT-based worst case delay estimation under process variation

Antoniadis C., Garyfallou D., Evmorfopoulos N., Stamoulis G. (2018)

Manufacturing process variation in sub-20nm processes has introduced ever increasing overhead in Static Timing Analysis (STA) in order to guarantee the reliable operation of the circuit. Chip designers apply corner-based ...

A Fast Timing Separation of Events Algorithm for Concurrent Systems

Aimoniotis P., Xiromeritis N., Sotiriou C. (2019)

In this work, we present a fast, polynomial time implementation of the Timing Separation of Events (TSE) Algorithm, with complexity O(E × (V+E). TSE computation is a fundamental problem in the analysis of event-driven, ...

Graph-Based STA for Asynchronous Controllers

Xiromeritis N., Simoglou S., Sotiriou C., Sketopoulos N. (2019)

In this work, we present an Asynchronous Static Timing Analysis (ASTA) EDA methodology for cyclic, Asynchronous Control Circuits. Our methodology operates using Graph-based Analysis (GBA) principles, as conventional ...

Graph-based STA for asynchronous controllers

Simoglou S., Xiromeritis N., Sotiriou C., Sketopoulos N. (2020)

We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its ...

Instruction-based timing analysis in pipelined processors

Tziouvaras A., Dimitriou G., Dossis M., Stamoulis G. (2019)

Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless ...

Instruction-Flow-Based Timing Analysis in Pipelined Processors

Tziouvaras A., Dimitriou G., Dossis M., Stamoulis G. (2019)

Microprocessor design utilizes timing analysis in order to establish the maximal operation clock speed of the circuit. In static timing analysis, clock frequency is set in accord with the worst-case delay in the circuit ...

On the Impact of Electrical Masking and Timing Analysis on Soft Error Rate Estimation in Deep Submicron Technologies

Tsoumanis P., Paliaroutis G.-I., Evmorfopoulos N., Stamoulis G. (2021)

Soft errors constitute a crucial reliability concern for the Integrated Circuits (ICs) as the continuous CMOS technology downscaling renders them vulnerable to radiation-induced hazards. Therefore, the Soft Error Rate (SER) ...

A power-supply noise aware dynamic timing analysis methodology, based on a statistical prediction engine

Tsiampas M., Evmorfopoulos N., Daloukas K., Moondanos J., Stamoulis G. (2018)

As technologies continue to shrink, industry seeks even faster ultra-low power ICs, requiring more accurate estimation of the worst case delay. Although traditional Static Timing Analysis (STA) methods incorporate data ...

STA for mixed cyclic, acyclic circuits

Simoglou S., Sotiriou C., Valiantzas D., Sketopoulos N. (2020)

In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology ...

Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits

Simoglou S., Sotiriou C., Blias N. (2021)

In this paper, we demonstrate that conventional Static Timing Anaysis (STA) based, functional, gate-level simulation of asynchronous circuits with cycles is only as accurate as the STA engine used. This is, firstly because ...