Πλοήγηση ανά Θέμα "SDRAM"
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A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration and slew rate control
(2012)A 1 GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driven has been developed for the first time to our knowledge using a 90 nm CMOS process. To satisfy the signal integrity requirements the ...