Πλοήγηση ανά Θέμα "Integrated circuit manufacture"
Αποτελέσματα 1-7 από 7
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Accelerating Electromigration Stress Analysis Using Low-Rank Balanced Truncation
(2022)Electromigration (EM) has become one of the most significant challenges considering longterm reliability in integrated circuit design. The problem is caused by the large current density in circuit interconnections. However, ... -
A Combinatorial Multigrid Preconditioned Iterative Method for Large Scale Circuit Simulation on GPU s
(2018)Efficient large scale circuit simulation is among the most challenging problems facing the EDA industry today, since it is the only feasible way to verify a circuit's behaviour prior to manufacturing. In recent years, the ... -
Efficient Circuit Reduction in Limited Frequency Windows
(2019)Model Order Reduction (MOR) has become key enabler for the efficient simulation of large circuit models. MOR techniques based on Balanced Truncation (BT) offer very good error estimates and can provide compact models with ... -
Efficient Hotspot Thermal Simulation Via Low-Rank Model Order Reduction
(2018)Efficient full-chip thermal simulation is among the most challenging problems facing the EDA industry today, due to the need for solution of very large systems of equations that require unreasonably long computational ... -
Global and Pointer Variables in High-Level Synthesis
(2020)High-level synthesis (HLS) has been an important tool in digital circuit design for more than two decades, especially for processor components like accelerators or coprocessors. However, many high-level language characteristics ... -
On the Sparsification of the Reluctance Matrix in RLCk Circuit Transient Analysis
(2018)The ever increasing frequency scaling of contemporary very large scale integrated circuits has introduced the necessity to factor in signal integrity the analysis of inductive effects arising within the different blocks ... -
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects
(2019)Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regimes, the fast and accurate timing analysis of interconnects has become ...