Listar por tema "Gate levels"
Mostrando ítems 1-2 de 2
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CAS-HtBase: a new database for the study of HTs at the pre-silicon stage of ASICs
(2022)Hardware Trojan (HT) consists a chip-level viruses which aim to leak encrypted information or degrade the performance of the infected device. They are a modification to the original design of a circuit and consist of two ... -
Leveraging Machine Learning for Gate-level Timing Estimation Using Current Source Models and Effective Capacitance
(2022)With process technology scaling, accurate gate-level timing analysis becomes even more challenging. Highly resistive on-chip interconnects have an ever-increasing impact on timing, signals no longer resemble smooth saturated ...