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Browsing by Subject "Standard cell design"

Now showing items 1-4 of 4

    • Enhanced tetris legalization 

      Dadaliaris A.N., Nerantzaki E., Oikonomou P., Hatzaras Y., Troumpoulou A.-O., Arvanitakis I., Stamoulis G.I. (2016)
      Legalization and detailed placement methods for standard cell designs, are two of the most notable topics in current VLSI research. Being the final steps in a classic placement procedure they must be efficient in terms of ...

    • Exploiting Net Connectivity in Legalization and Detailed Placement Scenarios 

      Dadaliaris A., Kranas G., Oikonomou P., Floros G., Dossis M. (2022)
      Standard-cell placement is the fundamental step in a typical VLSI/ASIC design flow. Its result, paired with the outcome of the routing procedure can be the decisive factor in rendering a design manufacturable. Global ...

    • PyPUT: Python-based Placement Utilities Toolset 

      Kranas G., Tsalamagkakis G.-C., Oikonomou P., Dadaliaris A.N. (2018)
      In the placement stage of a standard-cell design flow, a set of cells must be placed within a specified rectangular region, that may contain obstacles, in such a way that overlaps and overflows are non-existent and a target ...

    • Variations on a Connectivity-based Legalizer for Standard Cell Design 

      Dadaliaris A.N., Kranas G.K., Oikonomou P., Dossis M. (2021)
      Legalization is considered the most significant step in a placement correlated standard cell design flow as moving cells towards legal positions to avoid overlap among them may escalate the overall wire length. Monolithic ...