Browsing by Subject "Delay circuits"
Now showing items 1-9 of 9
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Constant delay systolic binary counter with variable size cellular automaton based prescaler
(2021)An One-Dimension (1D) Cellular Automaton (CA) is studied as a generator for the radix-2 sequence, presenting suitable characteristics for the design of a fast and constant delay synchronous digital counter. The main ... -
EVT-based worst case delay estimation under process variation
(2018)Manufacturing process variation in sub-20nm processes has introduced ever increasing overhead in Static Timing Analysis (STA) in order to guarantee the reliable operation of the circuit. Chip designers apply corner-based ... -
Experimental validation of the dual Kalman filter for online and real-time state and input estimation
(2015)In this study, a novel dual implementation of the Kalman filter is proposed for simultaneous estimation of the states and input of structures via acceleration measurements. In practice, the uncertainties stemming from the ... -
Instruction-based timing analysis in pipelined processors
(2019)Traditional timing analysis techniques for microprocessor design are based on the static analysis approach, in which clock frequency is set in accord with the worst-case delay in the processor circuit operation, regardless ... -
Instruction-Flow-Based Timing Analysis in Pipelined Processors
(2019)Microprocessor design utilizes timing analysis in order to establish the maximal operation clock speed of the circuit. In static timing analysis, clock frequency is set in accord with the worst-case delay in the circuit ... -
Simulation-Based Maximum Coverage Hazard Detection and Elimination Analysis, Supporting Combinational Logic Loops
(2022)We demonstrate an iterative simulation-based maximum coverage detection and elimination analysis of logic-hazards for combinational logic loops. Although the focus is on asynchronous circuits with such feedbacks, it is ... -
A Sparsity-Aware MOR Methodology for Fast and Accurate Timing Analysis of VLSI Interconnects
(2019)Signoff timing analysis is essential in order to verify the proper operation of VLSI circuits. As process technologies scale down towards nanometer regimes, the fast and accurate timing analysis of interconnects has become ... -
STA for mixed cyclic, acyclic circuits
(2020)In this work, we present a Static Timing Analysis (STA) methodology for cyclic circuits with attached acyclic datapaths, as an alternative to SPICE level electrical simulation, based on ASTA (Asynchronous STA). Our methodology ... -
Systolic binary counter using a cellular automaton-based prescaler
(2017)Counters are among the fundamental digital circuits in every computing system. For this reason, counter design is of great interest in the design of computers and embedded systems, in terms of area requirements,power ...