Garyfallou D., Simoglou S., Sketopoulos N., Antoniadis C., Sotiriou C.P., Evmorfopoulos N., Stamoulis G. (2021)
As process geometries shrink below 45 nm, accurate and efficient gate-level timing analysis becomes even more challenging. Modern VLSI interconnects are more resistive, signals no longer resemble saturated ramps, and gate ...