Εμφάνιση απλής εγγραφής

dc.creatorSketopoulos N., Sotiriou C.P., Samaras V.en
dc.date.accessioned2023-01-31T09:57:36Z
dc.date.available2023-01-31T09:57:36Z
dc.date.issued2019
dc.identifier10.1145/3299874.3319487
dc.identifier.isbn9781450362528
dc.identifier.urihttp://hdl.handle.net/11615/79089
dc.description.abstractIn this work, we compare alternative 3DIC partitioning methodologies, in terms of slack, number of inter-tier vias, Tier Area Ratio (TAR) and HPWL design parameters. The popular 3DIC postplacement, bin-based Fidducia-Mattheyses (FM) partitioning flow is used as a baseline for comparison. While the latter does produce a minimum number of inter-tier vias, for a specified FM area balance, their number cannot be directly constrained. This behavior motivated us to investigate a different 3DIC partitioning scheme, based on post-placement 3D legalisation, where the legaliser is capable of spreading cells across all available tiers for minimum displacement or HPWL. In contrast to bin-based FM, in 3D legalisation, the number of inter-tier vias can be directly constrained, albeit at the expense of TAR. The 3D legalisation partitioning scheme can expose a continuous trade off between the available number of intertier vias and design parameters. An unconstrained number of vias, which produce the best 3D gains in design parameters, while constraining the numbers of vias will trade them off with lower 3D gains. Results for three 3DIC partitioning flows are presented, on four OpenCores benchmarks, and the achieved trade offs between number of inter-tier vias and slack, TAR and HPWL parameters, per flow, are described. © 2019 ACM.en
dc.language.isoenen
dc.sourceProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSIen
dc.source.urihttps://www.scopus.com/inward/record.uri?eid=2-s2.0-85083256551&doi=10.1145%2f3299874.3319487&partnerID=40&md5=3dd4e6511380b84fbb96fe71212e0522
dc.subjectAuthenticationen
dc.subjectContractsen
dc.subjectFrequency modulationen
dc.subjectInformation disseminationen
dc.subjectTaren
dc.subjectThree dimensional integrated circuitsen
dc.subjectVLSI circuitsen
dc.subjectArea ratiosen
dc.subjectDesign parametersen
dc.subjectPartitioning flowen
dc.subjectTrade offen
dc.subjectEconomic and social effectsen
dc.subjectAssociation for Computing Machineryen
dc.titleInvestigation and trade-offs in 3DIC partitioning methodologies: N/Aen
dc.typeconferenceItemen


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Εμφάνιση απλής εγγραφής