| dc.creator | Sapounaki M., Kakarountas A. | en |
| dc.date.accessioned | 2023-01-31T09:53:54Z | |
| dc.date.available | 2023-01-31T09:53:54Z | |
| dc.date.issued | 2021 | |
| dc.identifier | 10.1109/MOCAST52088.2021.9493396 | |
| dc.identifier.isbn | 9781665418478 | |
| dc.identifier.uri | http://hdl.handle.net/11615/78783 | |
| dc.description.abstract | In recent years, scientists strove to create devices that may ameliorate patients' lives who suffer from a neuronal disease. These devices are mainly based on neuromorphic circuits and usually employ mathematical equations. This paper implements Izhikevich (IZH) mathematical model on an FPGA board. The paper proposes an innovative hardware architecture that creates an application-specific Processing Unit for implementing a neuron. The design achieves to decrease power consumption by 37,5% and 16% of the dynamic and the total power consumption, respectively, while maintaining the computational speed at the same level, compared to similar works. © 2021 IEEE. | en |
| dc.language.iso | en | en |
| dc.source | 2021 10th International Conference on Modern Circuits and Systems Technologies, MOCAST 2021 | en |
| dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85112185746&doi=10.1109%2fMOCAST52088.2021.9493396&partnerID=40&md5=6b2eb49aec2dfc9cdaf174ddb4a2bd36 | |
| dc.subject | Electric power utilization | en |
| dc.subject | Timing circuits | en |
| dc.subject | Application specific | en |
| dc.subject | Computational speed | en |
| dc.subject | FPGA boards | en |
| dc.subject | Hardware architecture | en |
| dc.subject | Mathematical equations | en |
| dc.subject | Neuromorphic circuits | en |
| dc.subject | Processing units | en |
| dc.subject | Total power consumption | en |
| dc.subject | Low power electronics | en |
| dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
| dc.title | A Novel Low-power Neuromorphic Circuit based on Izhikevich Model | en |
| dc.type | conferenceItem | en |