dc.creator | Koziri M., Papadopoulos P.K., Tziritas N., Giachoudis N., Loukopoulos T., Khan S.U., Stamoulis G.I. | en |
dc.date.accessioned | 2023-01-31T08:46:53Z | |
dc.date.available | 2023-01-31T08:46:53Z | |
dc.date.issued | 2017 | |
dc.identifier | 10.23919/EUSIPCO.2017.8081462 | |
dc.identifier.isbn | 9780992862671 | |
dc.identifier.uri | http://hdl.handle.net/11615/75489 | |
dc.description.abstract | HEVC has emerged as the new video coding standard promising increased compression ratios compared to its predecessors. This performance improvement comes at a high computational cost. For this reason, HEVC offers three coarse grained parallelization potentials namely, wave front, slices and tiles. In this paper we focus on tile parallelism which is a relatively new concept with its effects not yet fully explored. Particularly, we investigate the problem of partitioning a frame into tiles so that in a resulting one on one tile-CPU core assignment the cores are load balanced, thus, maximum speedup can be achieved. We propose various heuristics for the problem with a focus on low delay coding and evaluate them against state of the art approaches. Results demonstrate that particular heuristic combinations clearly outperform their counterparts in the literature. © EURASIP 2017. | en |
dc.language.iso | en | en |
dc.source | 25th European Signal Processing Conference, EUSIPCO 2017 | en |
dc.source.uri | https://www.scopus.com/inward/record.uri?eid=2-s2.0-85038932906&doi=10.23919%2fEUSIPCO.2017.8081462&partnerID=40&md5=e302a05e2c6e72d1b5e79206f4478822 | |
dc.subject | Codes (symbols) | en |
dc.subject | Image coding | en |
dc.subject | Signal processing | en |
dc.subject | Tile | en |
dc.subject | Wavefronts | en |
dc.subject | Computational costs | en |
dc.subject | HEVC | en |
dc.subject | Low-delay coding | en |
dc.subject | Parallelism | en |
dc.subject | Parallelization potential | en |
dc.subject | Partitioning | en |
dc.subject | State-of-the-art approach | en |
dc.subject | Video coding standard | en |
dc.subject | Video signal processing | en |
dc.subject | Institute of Electrical and Electronics Engineers Inc. | en |
dc.title | Heuristics for tile parallelism in HEVC | en |
dc.type | conferenceItem | en |