| dc.creator | Plessas, F. | en |
| dc.creator | Davrazos, E. | en |
| dc.creator | Alexandropoulos, A. | en |
| dc.creator | Birbas, M. | en |
| dc.creator | Kikidis, J. | en |
| dc.date.accessioned | 2015-11-23T10:45:46Z | |
| dc.date.available | 2015-11-23T10:45:46Z | |
| dc.date.issued | 2012 | |
| dc.identifier | 10.1016/j.compeleceng.2011.12.012 | |
| dc.identifier.issn | 0045-7906 | |
| dc.identifier.uri | http://hdl.handle.net/11615/32328 | |
| dc.description.abstract | A 1 GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driven has been developed for the first time to our knowledge using a 90 nm CMOS process. To satisfy the signal integrity requirements the driver strength is dynamically calibrated and the input/output port is efficiently terminated by on-die resistors. Furthermore, the slew-rate can be sufficiently controlled by selecting an appropriate external resistor. The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die area of 0.032 mm(2) (differential). Experimental results demonstrate its robustness over process, voltage, and temperature variations. (C) 2012 Elsevier Ltd. All rights reserved. | en |
| dc.source | Computers & Electrical Engineering | en |
| dc.source.uri | <Go to ISI>://WOS:000303094900003 | |
| dc.subject | SDRAM | en |
| dc.subject | Computer Science, Hardware & Architecture | en |
| dc.subject | Computer Science, | en |
| dc.subject | Interdisciplinary Applications | en |
| dc.subject | Engineering, Electrical & Electronic | en |
| dc.title | A 1 GHz, DDR2/3 SSTL driver with On-Die Termination, strength calibration and slew rate control | en |
| dc.type | journalArticle | en |
