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Implementation and performance comparison of the motion compensation kernel of the AVS video decoder on FPGA, GPU and multicore processors

dc.creatorOwaida, M.en
dc.creatorBellas, N.en
dc.creatorAntonopoulos, C. D.en
dc.creatorDaloukas, K.en
dc.creatorAntoniadis, C.en
dc.creatorKrommydas, K.en
dc.creatorTsoumblekas, G.en
dc.date.accessioned2015-11-23T10:41:57Z
dc.date.available2015-11-23T10:41:57Z
dc.date.issued2011
dc.identifier10.1109/FCCM.2011.32
dc.identifier.isbn9780769543017
dc.identifier.urihttp://hdl.handle.net/11615/31513
dc.description.abstractNext generation video standards have strict and increasing performance demands due to real-time requirements and the trend towards higher frame resolutions and bit rates. Leveraging the advantages of reconfigurable logic and emerging multi-core processor architectures to exploit all levels of parallelism of such workloads is necessary to achieve real time functionality at a reasonable cost. © 2011 IEEE.en
dc.source.urihttp://www.scopus.com/inward/record.url?eid=2-s2.0-79958712110&partnerID=40&md5=8280f929386bff01b2d1bb77dfcc9ce1
dc.subjectAVS Motion Compensationen
dc.subjectFPGAen
dc.subjectGPUen
dc.subjectMulti-coresen
dc.subjectReconfigurable Computingen
dc.subjectVideo Compressionen
dc.subjectBit ratesen
dc.subjectMulti-core processoren
dc.subjectPerformance comparisonen
dc.subjectReal timeen
dc.subjectReal time requirementen
dc.subjectReconfigurable logicen
dc.subjectVideo decodersen
dc.subjectVideo standarden
dc.subjectComputer architectureen
dc.subjectComputersen
dc.subjectField programmable gate arrays (FPGA)en
dc.subjectImage compressionen
dc.subjectReconfigurable hardwareen
dc.subjectMotion compensationen
dc.titleImplementation and performance comparison of the motion compensation kernel of the AVS video decoder on FPGA, GPU and multicore processorsen
dc.typeconferenceItemen


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