A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory

dc.creator	Maniotis, P.	en
dc.creator	Gitzenis, S.	en
dc.creator	Tassiulas, L.	en
dc.creator	Pleros, N.	en
dc.date.accessioned	2015-11-23T10:38:41Z
dc.date.available	2015-11-23T10:38:41Z
dc.date.issued	2014
dc.identifier	10.1109/OFC.2014.6886752
dc.identifier.isbn	9781557529930
dc.identifier.uri	http://hdl.handle.net/11615/30627
dc.description.abstract	We demonstrate a system-level CMP architecture where optical cache memories are shared among multiple processing cores through optical buses. System-level simulations show 25-45% execution time improvement and significant capacity requirements reduction through simpler memory hierarchy. © 2014 OSA.	en
dc.source.uri	http://www.scopus.com/inward/record.url?eid=2-s2.0-84907411190&partnerID=40&md5=de685b80ba7ec9e0db6d06492f729000
dc.subject	Capacity requirement	en
dc.subject	Chip-multiprocessor	en
dc.subject	CMP architectures	en
dc.subject	Memory hierarchy	en
dc.subject	Multiple processing cores	en
dc.subject	Optical bus	en
dc.subject	System level simulation	en
dc.subject	System levels	en
dc.subject	Cache memory	en
dc.title	A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memory	en
dc.type	conferenceItem	en

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