dc.creator | Dimitriou, G. | en |
dc.creator | Polychronopoulos, C. | en |
dc.date.accessioned | 2015-11-23T10:25:36Z | |
dc.date.available | 2015-11-23T10:25:36Z | |
dc.date.issued | 2005 | |
dc.identifier.isbn | 3-540-29673-5 | |
dc.identifier.issn | 0302-9743 | |
dc.identifier.uri | http://hdl.handle.net/11615/27074 | |
dc.description.abstract | Loop scheduling has significant differences in multithreaded from other parallel processors. The sharing of hardware resources imposes new scheduling limitations, but it also allows a faster communication across threads. We present a multithreaded processor model, Coral 2000, with hardware extensions that support Macro Software Pipelining, a loop scheduling technique for multithreaded processors. We tested and evaluated Coral 2000 on a cycle-level simulator, using synthetic and integer SPEC benchmarks. We obtained speedups of up to 30% with respect to highly optimized superblock-based schedules on loops that exhibit limited parallelism. | en |
dc.source.uri | <Go to ISI>://WOS:000233675500059 | |
dc.subject | COMPILATION | en |
dc.subject | Computer Science, Artificial Intelligence | en |
dc.subject | Computer Science, Information | en |
dc.subject | Systems | en |
dc.subject | Computer Science, Theory & Methods | en |
dc.subject | Telecommunications | en |
dc.title | Hardware support for multithreaded execution of loops with limited parallelism | en |
dc.type | bookChapter | en |